dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux

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On PolarFire SoC there are more GPIO interrupts than there are interrupt
lines available on the PLIC, and a runtime configurable mux is used to
decide which interrupts are assigned direct connections to the PLIC &
which are relegated to sharing a line.

Reviewed-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Conor Dooley 2026-03-18 11:04:34 +00:00

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103

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml

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4

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml

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