drm/msm: dpu: Only check flush register against pending flushes

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There exists a case where a flush of a plane/dma may have been triggered
& started from an async commit. If that plane/dma is subsequently disabled
by the next commit, the flush register will continue to hold the flush
bit for the disabled plane. Since the bit remains active,
pending_kickoff_cnt will never decrement and we'll miss frame_done
events.

This patch limits the check of flush_register to include only those bits
which have been updated with the latest commit.

Changes in v2:
- None

Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

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Sean Paul 2018-10-30 12:00:08 -04:00 • committed by Rob Clark

parent d4e98855d1

commit 5f79e03b1f

1 changed files with 1 additions and 1 deletions

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2

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

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