Addition of the CPU clock configuration data for Exynos4412

Browse source

Prime SoC variant.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJYZS0+AAoJEE1bIKeAnHqL/dgP+gM1HRhx/EEgCtWlUezdTQiV
 kdVEuvMi6/uVC4h4ElG52q3yhsT3A949Fge+I4HKvFfNhwYhA6OGfF2CY/uSSt7W
 GgV9yZxnfAuRM6IBIhCfh4DPczhCDAZiViYzWT2qkMA2H8in134b3nug/aF3cINI
 OeJNkrVseVZe5jmaTG+NsPPwh9/2t2lTA5tJ40P7JTb7oneC2Q4JEfz/vqx75RNv
 6/w5Ve4Kz1L3oXcAWx3OxUUfK9Obi2xeH6lXttSKdcezTT0aMYLnehnkl/3A3qTC
 P24c5CzoFA62VL1pq+Aq2/r2loHKo1Sm6PnBCw/cWz9dAtU2lch6RySbk5cY2vgu
 5N0J7vtuP9XevuepmWeNJfB130FvJVPuLGUiDED7TEFE0DtmY/hHAJm8f/qNpvp6
 qbE2Tb9HTUQlykSX7c2cD5HruOB0lKBpEgPhBfregVX/oJ+dtxFwNcna051prXUy
 z+YWEWeHkDGaZeaRej0r4S7o6ebp+S+fOivqpRY5p+9fGCF47ZgwbUE8PwPssyXE
 12mp5getjtnVUgrrWhSmpxKNC/RYs/6W2k4iO4WMXc2TxHF21NfFtQwCzjTDDuFR
 /x6OdoDQ9Cp8eaBiwNqzYqlcKv6wr5oK0sdljb5XWjAa96KmIECmxCMnc4aB+c3n
 tPwryTHL5gNYalTQGaCB
 =bMk6
 -----END PGP SIGNATURE-----

Merge tag 'clk-v4.11-exynos4-pll' of git://linuxtv.org/snawrocki/samsung into next/dt

Addition of the CPU clock configuration data for Exynos4412
Prime SoC variant.

...

This commit is contained in:

Krzysztof Kozlowski 2016-12-30 16:44:05 +02:00

parent 3590312f47 c369596f89

commit 5fab38e932

1 changed files with 4 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

4

drivers/clk/samsung/clk-exynos4.c

View file