clk: renesas: r9a09g077: Add SPI module clocks

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The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have four SPI
peripherals, each with their own clock divider, which divides PLL4 by
either 24, 25, 30 or 32, similar to the SCI peripheral.

The dividers feed into the usual module clocks.

Add them all.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251105104151.1489281-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Cosmin Tanislav 2025-11-05 12:41:38 +02:00 • committed by Geert Uytterhoeven

parent 7efa3a6d96

commit 5fb2f67341

1 changed files with 21 additions and 1 deletions

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drivers/clk/renesas/r9a09g077-cpg.c

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