qed: Configure cacheline size in HW

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Default HW configuration is optimal for an architecture where cache
line size is 64B.

During chip initialization, properly initialize the cache line size
in HW to avoid possible redundant PCI transactions.

Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Tomer Tayar 2017-04-06 15:58:30 +03:00 • committed by David S. Miller

parent 1558296251

commit 60afed72f5

2 changed files with 54 additions and 0 deletions

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53

drivers/net/ethernet/qlogic/qed/qed_dev.c

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1

drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

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