PCI: dwc: Work around ECRC configuration issue

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DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a.

[bhelgaas: fix typos/grammar errors]
Link: https://lore.kernel.org/r/20201230165723.673-1-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>

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Vidya Sagar 2020-12-30 22:27:23 +05:30 • committed by Bjorn Helgaas

parent 7c53f6b671

commit 6104033bd2

2 changed files with 48 additions and 2 deletions

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49

drivers/pci/controller/dwc/pcie-designware.c

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1

drivers/pci/controller/dwc/pcie-designware.h

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