drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disabling

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While disabling Thunderbolt PLL, we request PLL to be stopped and
wait for ACK bit to be cleared. The expected value should be '0'
instead of '~XELPDP_TBT_CLOCK_ACK' or otherwise we incorrectly
receive dmesg warn "PHY PLL not unlocked in 10us".

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230512120003.587360-1-mika.kahola@intel.com

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Mika Kahola 2023-05-12 15:00:03 +03:00 • committed by Radhakrishna Sripada

parent 9c3a985f88

commit 615ed9ece0

1 changed files with 1 additions and 3 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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