clk: lmk04832: add support for digital delay

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The digital delay allows outputs to be delayed from 8 to 1023 VCO
cycles. The delay step can be as small as half the period of the clock
distribution path. For example, a 3.2-GHz VCO frequency results in
156.25-ps steps.  The digital delay value takes effect on the clock
output phase after a SYNC event.

This is required to support JESD204B subclass 1.

Signed-off-by: Liam Beguin <lvb@xiphos.com>
Link: https://lore.kernel.org/r/20210423004057.283926-3-liambeguin@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Liam Beguin 2021-04-22 20:40:56 -04:00 • committed by Stephen Boyd

parent 3bc61cfd6f

commit 6181baa177

1 changed files with 315 additions and 6 deletions

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drivers/clk/clk-lmk04832.c

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