clk: sunxi: Add mod0 and mmc module clock support for A80

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The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2015-01-17 13:19:26 +08:00 • committed by Maxime Ripard

parent eb378df79e

commit 61af4d8dce

2 changed files with 37 additions and 2 deletions

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7

Documentation/devicetree/bindings/clock/sunxi.txt

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32

drivers/clk/sunxi/clk-mod0.c

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