drm/i915: Make the pipe/output CSC register writes lockless

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The pipe/output CSC register writes don't need to be locked
since all the registers are suitably isolated to their own
cachelines. So eliminate the locks to reduce the overhead
during the vblank evade critical section.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220202111616.1579-2-ville.syrjala@linux.intel.com
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

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Ville Syrjälä 2022-02-02 13:16:14 +02:00

parent f470b218b0

commit 61b3b2da10

1 changed files with 40 additions and 40 deletions

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drivers/gpu/drm/i915/display/intel_color.c

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