drm/i915/snps: use div32 version of MPLLB word clock for UHBR

Browse source

The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.

Bspec: 53880, 54128
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com

...

This commit is contained in:

Jani Nikula 2021-12-02 16:44:56 +02:00

parent 1c7ab5affa

commit 61b98486e4

2 changed files with 3 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

drivers/gpu/drm/i915/display/intel_snps_phy.c

View file

1

drivers/gpu/drm/i915/i915_reg.h

View file