drm/amd/display: Add driver-side parsing for CM

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Although 4 unique register values exist for gamma modes, two are
actually the same (the two RAMs) It’s not possible for caller to
understand this HW specific behavior, so some parsing is necessary
in driver

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Jun Lei 2018-08-13 15:11:44 -04:00 • committed by Alex Deucher

parent 550db28812

commit 61ea4c6f70

1 changed files with 25 additions and 4 deletions

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29

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

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