MIPS: lantiq: split up IRQ IM ranges

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Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/

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This commit is contained in:

John Crispin 2012-08-16 11:39:57 +00:00

parent fea7a08acb

commit 61fa969f27

3 changed files with 36 additions and 28 deletions

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2

arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h

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2

arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h

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60

arch/mips/lantiq/irq.c

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