arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts

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Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers.  Drop the masks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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Geert Uytterhoeven 2026-03-04 18:11:02 +01:00 • committed by Dinh Nguyen

parent bb5f66f36b

commit 625af11fb9

1 changed files with 4 additions and 4 deletions

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arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

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