can: mcp251xfd: ring: change order of TX and RX FIFOs

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This patch actually changes the order of the TX and RX FIFOs.

This gives the opportunity to minimize the number of SPI transfers in
the IRQ handler. The read of the IRQ status register and RX FIFO
status registers can be combined into single SPI transfer. If the RX
ring uses FIFO 1, the overall length of the transfer is smaller than
in the original layout, where the RX FIFO comes after the TX FIFO.

Link: https://lore.kernel.org/all/20220217103826.2299157-5-mkl@pengutronix.de
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

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Marc Kleine-Budde 2021-08-03 16:33:48 +02:00

parent 617283b9c4

commit 62713f0d9a

2 changed files with 2 additions and 2 deletions

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2

drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c

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2

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

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