clk: renesas: rzg2l: Add divider clock for RZ/G3S

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Add a divider clock driver for RZ/G3S.  This will be used on RZ/G3S for
the SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, and P3 core clocks.
The divider has some limitation for SDHI, OCTA and SPI clocks:
  - SDHI div cannot be 1 if parent rate is 800MHz,
  - OCTA, SPI div cannot be 1 if parent rate is 400MHz.
To handle these limitations, a notifier is registered from platform
specific clock driver, which makes sure proper actions are taken before
the clock rate is changed, when needed.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231006103959.197485-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Claudiu Beznea 2023-10-06 13:39:58 +03:00 • committed by Geert Uytterhoeven

parent 16b86e5c03

commit 62b1feac48

2 changed files with 197 additions and 0 deletions

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186

drivers/clk/renesas/rzg2l-cpg.c

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11

drivers/clk/renesas/rzg2l-cpg.h

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