drm/i915: Only enable DDI IO power domains after enabling DPLL

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According to bspec, the DDI IO power domains should be enabled after
enabling the DPLL and mapping it to the DDI. The current order doesn't
seem to create problems with Skylake and Kabylake, but causes enable
timeouts in Geminilake.

v2: Rebase.
  - Take power domain references before sanitizing encoders. (Imre)
  - Add comment to get_encoder_power_domains() defition. (Ander)

v3: Don't put the domain if called with HSW/BDW's analog encoder. (CI)

v4: Put IO power domain before unmapping DPLL. (Imre)
  - Change return type of intel_ddi_get_power_domains() to u64. (Imre)

Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> # v1
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170224141959.5955-1-ander.conselvan.de.oliveira@intel.com

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This commit is contained in:

Ander Conselvan de Oliveira 2017-02-24 16:19:59 +02:00

parent 71cc22e5db

commit 62b695662a

5 changed files with 117 additions and 29 deletions

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5

drivers/gpu/drm/i915/i915_drv.h

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49

drivers/gpu/drm/i915/intel_ddi.c

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20

drivers/gpu/drm/i915/intel_display.c

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4

drivers/gpu/drm/i915/intel_drv.h

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68

drivers/gpu/drm/i915/intel_runtime_pm.c

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