MIPS: introduce CPU_R4K_CACHE_TLB

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R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>

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Florian Fainelli 2012-01-31 18:18:45 +01:00 • committed by John Crispin

parent 91405eb69e

commit 62cedc4fde

2 changed files with 5 additions and 16 deletions

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4

arch/mips/Kconfig

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17

arch/mips/mm/Makefile

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