clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs

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The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.

Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.

Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Icenowy Zheng 2017-09-10 20:40:05 +08:00 • committed by Maxime Ripard

parent 2bd6bf03f4

commit 62d212bdb0

1 changed files with 9 additions and 9 deletions

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18

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

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