drm/amd/display: fix dcn315 memory channel count and width read

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[Why & How]
Correctly set ddr5 channel width to 8 bytes

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Dmytro Laktyushkin 2022-08-30 15:16:40 -04:00 • committed by Alex Deucher

parent 22c42b0ec2

commit 62f0576c42

2 changed files with 7 additions and 3 deletions

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3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

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7

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

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