drm/msm/a6xx: Flush LRZ cache before PT switch

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[ Upstream commit 180349b840 ]

As per the recommendation, A7x and newer GPUs should flush the LRZ cache
before switching the pagetable. Update a6xx_set_pagetable() to do this.
While we are at it, sync both BV and BR before issuing  a
CP_RESET_CONTEXT_STATE command, to match the downstream sequence.

Fixes: af66706acc ("drm/msm/a6xx: Add skeleton A7xx support")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688995/
Message-ID: <20251118-kaana-gpu-support-v4-2-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Akhil P Oommen 2025-11-18 14:20:29 +05:30 • committed by Greg Kroah-Hartman

parent 4f4f7b5797

commit 630f2ce9c7

1 changed files with 8 additions and 2 deletions

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drivers/gpu/drm/msm/adreno/a6xx_gpu.c

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