drm/amd/display: cache pwl params and scl_data to avoid extra programming

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This saves us about 5000 reg writes per full update. This translates to about
40000 writes over the course of single eDP bootup.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Dmytro Laktyushkin 2017-10-27 17:55:03 -04:00 • committed by Alex Deucher

parent 069d418f41

commit 6334ac93a1

5 changed files with 30 additions and 38 deletions

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41

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

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6

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

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3

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

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10

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

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8

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

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