drm/xe/guc: Port Wa_22012727170/Wa_22012727685 to xe_wa

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Wa_22012727170 and Wa_22012727685 apply to DG2 using the same action and
conditions. Add both to the oob rules so they are both reported as
active.

Do not Wa_22012727170 to PVC and MTL since only early A* steppings are
affected.

v2: Remove DG2_G10 from Wa_22012727685 to match current WA database
    (Matt Roper)
v3: GRAPHICS_STEP(A0, FOREVER) can be left alone for DG2 as this means
    all steppings

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230526164358.86393-18-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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Lucas De Marchi 2023-05-26 09:43:54 -07:00 • committed by Rodrigo Vivi

parent bb0f2e05ad

commit 63bbd800ff

2 changed files with 4 additions and 7 deletions

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8

drivers/gpu/drm/xe/xe_guc.c

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3

drivers/gpu/drm/xe/xe_wa_oob.rules

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