usb: dwc3: core: Enable GUCTL1 bit 10 for fixing termination error after resume bug

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When configured in HOST mode, after issuing U3/L2 exit controller fails
to send proper CRC checksum in CRC5 field. Because of this behavior
Transaction Error is generated, resulting in reset and re-enumeration of
usb device attached. Enabling chicken bit 10 of GUCTL1 will correct this
problem.

When this bit is set to '1', the UTMI/ULPI opmode will be changed to
"normal" along with HS terminations, term, and xcvr signals after EOR.
This option is to support certain legacy UTMI/ULPI PHYs.

Added "snps,resume-hs-terminations" quirk to resolved the above issue.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Link: https://lore.kernel.org/r/20220920052235.194272-3-piyush.mehta@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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This commit is contained in:

Piyush Mehta 2022-09-20 10:52:35 +05:30 • committed by Greg Kroah-Hartman

parent 031cba1695

commit 63d7f9810a

2 changed files with 21 additions and 0 deletions

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17

drivers/usb/dwc3/core.c

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4

drivers/usb/dwc3/core.h

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