drm/xe/xe3p_lpg: Add MCR steering

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Xe3p_LPG has nearly identical steering to Xe2 and Xe3.  The only
DSS/XeCore change from those IPs is an additional range from
0xDE00-0xDE7F that was previously reserved, so we can simply grow one of
the existing ranges in the Xe2 table to include it.  Similarly, the
"instance0" table is also almost identical, but gains one additional
PSMI range and requires a separate table.

v2:
  - Drop reserved range from MEMPIPE range. (Dnyaneshwar)

Bspec: 75242
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patch.msgid.link/20260206-nvl-p-upstreaming-v3-5-636e1ad32688@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

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Matt Roper 2026-02-06 15:36:01 -03:00 • committed by Gustavo Sousa

parent f3e5f71fd6

commit 641a2208c0

1 changed files with 17 additions and 1 deletions

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drivers/gpu/drm/xe/xe_gt_mcr.c

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