From 6497a922e7155d2b794ae19feadbe50c23a0fa5a Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 21 Sep 2026 15:15:07 -0400 Subject: [PATCH] drm/amd/display: Fix zero dlg_reg write to program_ext_vblank [why] fix some non initialized reg_offset allow z8_only to program_ext_vblank [CLEANED] for dml2.1, dlg_reg moved inside hubp_reg add current_compbuf_size check ensure HW state reached. Partial application: DCN42 register-list additions only. Fixes: 0a5e0416e191 ("drm/amd/display: Add DCN42B code to DC") Fixes: 002f32db0d42 ("drm/amd/display: Fix dcn401_optimize_bandwidth") Signed-off-by: Charlene Liu Signed-off-by: Fangzhi Zuo Reviewed-by: Dmytro Laktyushkin Reviewed-by: Leo Chen Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h index 926ddc156a2b..f74d5690c89d 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h @@ -114,7 +114,12 @@ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\ - SR(DCHUBBUB_ARB_QOS_FORCE) + SR(DCHUBBUB_ARB_QOS_FORCE),\ + SR(DCHUBBUB_TEST_DEBUG_INDEX),\ + SR(DCHUBBUB_TEST_DEBUG_DATA),\ + SR(DCHUBBUB_CTRL_STATUS),\ + SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1),\ + SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2)\ #define HUBBUB_MASK_SH_LIST_DCN4_2(mask_sh)\ HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \