From 65121d706ecd9c7b1365f91cc9f4e3c01fd9f15b Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Jul 2026 15:06:33 +0300 Subject: [PATCH] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1046A SoC. The nodes are left disabled at the SoC level; board DTs will be expected to enable them once the consumer Ethernet nodes appear. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 6fefe837f434..270a97711a69 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -424,6 +424,66 @@ clock-names = "sfp"; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls1046a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls1046a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>;