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tg3: Add memory barriers to sync BD data
for weak memory model architectures to ensure that the chip will DMA valid BD data. Signed-off-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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