clk: renesas: rzg2l: Simplify SAM PLL configuration macro

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Replace the PLL146_CONF() macro and its associated CPG_SAMPLL_CLK{1,2}(n)
helpers with a single CPG_SAM_PLL_CONF(stby) macro that takes the PLL
standby register offset directly.

This removes the implicit coupling between PLL index n and register layout
and eliminates the now-redundant GET_REG_SAMPLL_CLK2() macro. The RZ/V2M
PLL4 definition is also updated to use the new macro with its explicit
standby offset (0x100), removing the local PLL4_CONF define.

No functional changes.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260519141518.389670-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Biju Das 2026-05-19 15:15:13 +01:00 • committed by Geert Uytterhoeven

parent 4f42053949

commit 6549ef9cc2

5 changed files with 10 additions and 16 deletions

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2

drivers/clk/renesas/r9a07g043-cpg.c

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drivers/clk/renesas/r9a07g044-cpg.c

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drivers/clk/renesas/r9a09g011-cpg.c

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drivers/clk/renesas/rzg2l-cpg.c

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drivers/clk/renesas/rzg2l-cpg.h

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