drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0

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Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Tim Huang 2022-08-15 13:03:49 +08:00 • committed by Alex Deucher

parent d6c770d205

commit 6575eb930d

2 changed files with 15 additions and 0 deletions

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2

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h

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13

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h

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