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MIPS KVM Guest FPU & SIMD (MSA) Support
Add guest FPU and MIPS SIMD Architecture (MSA) support to MIPS KVM, by enabling the host FPU/MSA while in guest mode. This adds two new KVM capabilities, KVM_CAP_MIPS_FPU & KVM_CAP_MIPS_MSA, and supports the 3 FP register modes (FR=0, FR=1, FRE=1), and 128-bit MSA vector registers, with lazy FPU/MSA context save and restore. Some required MIPS FP/MSA fixes are merged in from a branch in the MIPS tree first. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJVFc3aAAoJEGwLaZPeOHZ6DjwQAI4yYxOD3QmyIGMekQpFj3iE 5DhOpkXGTC6UHm2bI9ftvfkpfRVTc3ow4EnY+ytx4YIXjSnNn/xHnYmNJxVWQimQ jPCUuTQhPTX7BcYd/TGwu6inXe3f1I0vP7oLXUXA239wc/b/Y6KOfYJdewEGefqC 2kPxd/Towtx+HfGb8bicXYpHYDP0JrFfUClDtCHIsWmm2tlv4rkT0TD9gkhRjkP+ hQTyZlWF2279Cmk2c+r5ou7HRqK2EnUnry1N5YuY7+hKnqBvMW3mD8XNMvzIqKIJ CksFLKtHBx4OJojP3q6HX5BYFRzCItG3uUirQ3xZTzjZBEl8nKTKWIAoPtT7STgu qe9WCIelMvLp0tW1zVodS1L9tYXm2ijbqcrzAM0XaaysBiT3YrgN6R/m8fHyT3VP 0oqg8ozUTLPj6kjH6CsVAgjLhRvWFCZB+YH8kqRphmLXOXCWDmkdbaLL16R7kjGQ ajsx9lSkqFicUgycTpmlXlY6VdvPMekGbxBewf2H6PMuVHIO3LPnD80Z190yoMZs 9KzNQAFoy2uJs4nHVupa+dgqViQHMFt4wFGLg9+qnolcclA9PCQ/6nnMqSc2jQJ7 B8UGqesUR5j/9KD6vXE6Y9v7qZtTEc7NLwWVVfzXaHRmBIaFlWP9o0rJnFm3pGsZ WDC/bktf1XzCsHvCwIrS =jsOv -----END PGP SIGNATURE----- Merge tag 'kvm_mips_20150327' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/kvm-mips into kvm-next MIPS KVM Guest FPU & SIMD (MSA) Support Add guest FPU and MIPS SIMD Architecture (MSA) support to MIPS KVM, by enabling the host FPU/MSA while in guest mode. This adds two new KVM capabilities, KVM_CAP_MIPS_FPU & KVM_CAP_MIPS_MSA, and supports the 3 FP register modes (FR=0, FR=1, FRE=1), and 128-bit MSA vector registers, with lazy FPU/MSA context save and restore. Some required MIPS FP/MSA fixes are merged in from a branch in the MIPS tree first.
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