RISC-V: Detect Zicond from ISA string

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The RISC-V integer conditional (Zicond) operation extension defines
standard conditional arithmetic and conditional-select/move operations
which are inspired from the XVentanaCondOps extension. In fact, QEMU
RISC-V also has support for emulating Zicond extension.

Let us detect Zicond extension from ISA string available through
DT or ACPI.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>

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Anup Patel 2023-09-15 14:09:44 +05:30 • committed by Anup Patel

parent a4f5f39849

commit 662a601aa3

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arch/riscv/include/asm/hwcap.h

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arch/riscv/kernel/cpufeature.c

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