clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset

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The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.

Fix this problem.

Fixes: 0380126eb9 ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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Icenowy Zheng 2019-03-14 19:21:08 +08:00 • committed by Maxime Ripard

parent ab65e04dc1

commit 6630aad719

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drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c

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