clk: aspeed: Handle inverse polarity of USB port 1 clock gate

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The USB port 1 clock gate control has an inversed polarity
from all the other clock gates in the chip. This makes the
aspeed_clk_{enable,disable} functions honor the flag
CLK_GATE_SET_TO_DISABLE and set that flag appropriately
so it's set for all clocks except USB port 1.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Benjamin Herrenschmidt 2018-01-12 16:48:01 +11:00 • committed by Stephen Boyd

parent accf475a5e

commit 6671507f0f

1 changed files with 12 additions and 3 deletions

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drivers/clk/clk-aspeed.c

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