dt-bindings: riscv: Add Nuclei UX900 compatibles

Browse source

The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC.
It features a 64-bit architecture and dual-issue, 9-stage pipeline, with
lots of optional extensions including V, K, Zc, and more.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

...

This commit is contained in:

Junhui Liu 2025-10-21 17:41:37 +08:00 • committed by Conor Dooley

parent c86ee66e14

commit 66c2a3173c

1 changed files with 1 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

1

Documentation/devicetree/bindings/riscv/cpus.yaml

View file