clk: bcm2835: pll_off should only update CM_PLL_ANARST

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bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>

...

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Martin Sperl 2016-02-29 11:39:17 +00:00 • committed by Eric Anholt

parent 4d3ac66624

commit 6727f086cf

1 changed files with 8 additions and 2 deletions

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drivers/clk/bcm/clk-bcm2835.c

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