clk: uniphier: fix DAPLL2 clock rate of Pro5

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The parent of DAPLL2 should be DAPLL1.  Fix the clock connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Masahiro Yamada 2017-10-05 11:32:59 +09:00 • committed by Stephen Boyd

parent 3a5dfa7d78

commit 67affb78a4

1 changed files with 1 additions and 1 deletions

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drivers/clk/uniphier/clk-uniphier-sys.c

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