clk: renesas: r9a07g044: Add DSI clock and reset entries

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Add DSI clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2022-04-30 12:41:56 +01:00 • committed by Geert Uytterhoeven

parent 6f6178f1e1

commit 67f80edf83

1 changed files with 16 additions and 1 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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