clk: rockchip: rk3568: Add PLL rate for 126.4MHz

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Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel
can run at a requested 60hz.

I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Chris Morgan 2023-12-04 12:57:17 -06:00 • committed by Heiko Stuebner

parent 48794cd57a

commit 685da69726

1 changed files with 1 additions and 0 deletions

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drivers/clk/rockchip/clk-rk3568.c

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