drm/amd/display: Implement FIFO enable sequence on DCN32

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[WHY?]
FIFO enable sequence is incomplete as it is currently implemented in FW,
and requires reset to prevent the FIFO to be enabled in an invalid
state. This cannot be done until DIG FE is connected to the BE.

[HOW?]
Add FIFO enable sequence in driver for dcn32 with reset after DIG FE is
connected to BE.

Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Dillon Varone 2022-12-12 13:23:00 -05:00 • committed by Alex Deucher

parent 5ca3dc2b98

commit 689932a8dd

1 changed files with 28 additions and 0 deletions

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drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c

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