clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor

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The DDR1 PLL on the A33 is an oddball amongst the A33 CCU clocks.
It is a clock multiplier, with the effective multiplier in the
range of 12 ~ 255 and no offset between the multiplier value and
the value programmed into the register.

Implement the zero offset and minimum value of 12 for this clock.

Fixes: d05c748bd7 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2017-04-05 14:37:44 +08:00 • committed by Maxime Ripard

parent 25eb035c3f

commit 68f37d8624

1 changed files with 11 additions and 7 deletions

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drivers/clk/sunxi-ng/ccu-sun8i-a33.c

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