clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates

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Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Marek Szyprowski 2017-01-26 13:37:53 +01:00 • committed by Sylwester Nawrocki

parent 5ccb58968b

commit 698e0d1d22

1 changed files with 2 additions and 0 deletions

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drivers/clk/samsung/clk-exynos5433.c

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