drm/i915/ehl/dsi: Set lane latency optimization for DW1

Browse source

EHL has 2 additional steps in the DSI sequence, this is one of then
the lane latency optimization for DW1.

BSpec: 20597
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619233134.20009-1-jose.souza@intel.com

...

This commit is contained in:

Vandita Kulkarni 2019-06-19 16:31:33 -07:00 • committed by José Roberto de Souza

parent 60a0933bff

commit 6a7bafe8fd

2 changed files with 15 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

13

drivers/gpu/drm/i915/display/icl_dsi.c

View file

2

drivers/gpu/drm/i915/i915_reg.h

View file