ARM: dts: dra7: fix cpsw mdio fck clock

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The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)
is specified incorrectly, which is caused incorrect MDIO bus clock
configuration MDCLK. The correct CPSW MDIO functional clock is
gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.

Fixes: 1faa415c9c ("ARM: dts: Add fck for cpsw mdio for omap variants")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

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Grygorii Strashko 2019-11-18 14:20:16 +02:00 • committed by Tony Lindgren

parent e415e4d2d5

commit 6af0a549c2

1 changed files with 1 additions and 1 deletions

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arch/arm/boot/dts/dra7-l4.dtsi

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