x86/fpu: Cache xfeature flags from CPUID

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In preparation for runtime calculation of XSAVE offsets cache the feature
flags for each XSTATE component during feature enumeration via CPUID(0xD).

EDX has two relevant bits:
    0	Supervisor component
    1	Feature storage must be 64 byte aligned

These bits are currently only evaluated during init, but the alignment bit
must be cached to make runtime calculation of XSAVE offsets efficient.

Cache the full EDX content and use it for the existing alignment and
supervisor checks.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220324134623.573656209@linutronix.de

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Thomas Gleixner 2022-03-24 14:47:12 +01:00 • committed by Borislav Petkov

parent 35a77d4503

commit 6afbb58cc2

1 changed files with 13 additions and 36 deletions

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arch/x86/kernel/fpu/xstate.c

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