clk: sunxi: Rework MMC phase clocks

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Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Mike Turquette <mturquette@linaro.org>

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This commit is contained in:

Maxime Ripard 2014-12-07 17:43:04 +01:00

parent 3ec72fabcc

commit 6b0b8ccff0

2 changed files with 77 additions and 67 deletions

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13

Documentation/devicetree/bindings/clock/sunxi.txt

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121

drivers/clk/sunxi/clk-mod0.c

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