mlxsw: reg: Add to SFMR register the fields related to CFF flood mode

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Add the field cff_mid_base, which specifies at which point in PGT the
per-FID flood table is stored. Add cff_prf_id, the profile ID, which
determines on which row of the flood table a flood vector can be found for
a given traffic type.

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/3ad7ae38cf6534bedcd876f16090d109a814b3e3.1700503644.git.petrm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

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Petr Machata 2023-11-20 19:25:25 +01:00 • committed by Jakub Kicinski

parent 446bc1e9de

commit 6b10371c38

1 changed files with 20 additions and 0 deletions

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drivers/net/ethernet/mellanox/mlxsw/reg.h

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