perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT}

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IbsDcMissLat indicates the number of clock cycles from when a miss is
detected in the data cache to when the data was delivered to the core.
Similarly, IbsTagToRetCtr provides number of cycles from when the op
was tagged to when the op was retired. Consider these fields for
sample->weight.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20220928095805.596-5-ravi.bangoria@amd.com

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Ravi Bangoria 2022-09-28 15:27:54 +05:30 • committed by Peter Zijlstra

parent 7c10dd0a88

commit 6b2ae4952e

1 changed files with 16 additions and 1 deletions

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arch/x86/events/amd/ibs.c

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