clk: meson: axg: add the fractional part of the fixed_pll

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The fixed_pll also has a fractional part. On axg s400 board, without
this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll
being the root of the peripheral clock tree, this error is propagated to
the rest of the clocks

Adding the definition of the parameter fixes the problem

Fixes: 78b4af312f ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Jerome Brunet 2018-01-19 16:55:29 +01:00

parent 07f45e2ecc

commit 6b71aceceb

1 changed files with 5 additions and 0 deletions

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drivers/clk/meson/axg.c

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