Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi

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Allwinner sunXi SoCs clock changes

This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.

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This commit is contained in:

Mike Turquette 2013-12-29 13:37:56 -08:00

parent ea72dc2cf9 6f86341726

commit 6b71e0d9d6

4 changed files with 445 additions and 79 deletions

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10

Documentation/devicetree/bindings/clock/sunxi.txt

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63

drivers/clk/sunxi/clk-factors.c

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16

drivers/clk/sunxi/clk-factors.h

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435

drivers/clk/sunxi/clk-sunxi.c

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